The present invention relates to a clock signal generation apparatus, and more in particular to a clock signal generation apparatus suitable for generating a video signal accurately corresponding to the scanning start position of a scanning beam for a laser beam printer.
In a laser beam printer, as shown in FIG. 1, a video amplifier 1 amplifies a video signal produced from a video signal generation circuit 11 thereby to drive a laser diode 2. The laser light produced from the laser diode 2 is shaped by a coupling lens 3 into a laser beam, deflected by a polygon mirror 5 rotated at high speed by a scanner motor 4, and scans and exposes the surface of a light-sensitive drum 7 through an F-.theta. lens 6. The light-sensitive drum 7, which is rotating at a fixed speed, forms a toner image on the recording paper by a series of xerographic process including charging, exposure by scanning, development and transfer. The toner image on the recording paper is fixed and used.
In this laser beam printer, in order to synchronize the timing of starting the exposure by scanning with the timing of generating the video signal, the timing of the laser beam passing the scanning start reference position is detected by a photo sensor 8 making up a scanning beam detector, and an output signal of the photo sensor 8 is amplified by a sensor amplifier 9 thereby to produce a sync timing signal, that is, a beam detecting (BDT) signal. A scanning phase sync circuit 10 making up a clock signal generation unit generates a video clock signal synchronous with the sync timing signal, and an image shown in FIG. 2 or FIG. 3A is recorded on the basis of the video clock signal. In view of the fact that this video clock signal is formed by utilizing an original clock signal produced from a fixed frequency oscillation circuit, however, it is difficult to match the phase of the sync timing signal with that of the original clock signal at each starting time point of horizontal scanning, thus causing an out-of-phase condition (phase difference) within a range of one cycle of clock signal between the two signals.
Specifically, in a conventional clock signal generation apparatus disclosed in JP-A-56-126378 as shown in FIG. 3, for example, the timing of frequency division of the original clock signal is controlled in response to a sync timing signal. In other words, in response to, say, the rise of an original clock signal immediately after generation of a sync timing signal (BDT signal), the frequency division of the original clock signal is started thereby to produce a video clock. Regardless of whether the BDT signal is generated at a time point t.sub.1 indicated by solid line or at a time point t.sub.2 indicated by dotted line, therefore, the original clock signal starts being frequency-divided from a time point t.sub.3, so that there occurs a phase difference of one cycle of the clock signal at maximum between the sync timing signal and the video clock signal.
This phase difference is presented, as shown in FIG. 3B, as a displacement .DELTA.d of recording pixels along the horizontal scanning direction between horizontal scanning lines of the laser beam. In the case shown in FIG. 4, for example, if a clock signal whose frequency is divided to one eighth of a clock frequency f.sub.c is used as a video clock signal, the maximum phase difference becomes one eighth of the period of the video clock. In other words, the displacement .DELTA.d of recording pixels is one-eighth of one dot at maximum, where one dot equals to the width of one pixel.
Generally, in order to perform the recording of pixels with a high-definition, the displacement of the recording pixels .DELTA.d is preferably less than about one eighth of a dot. In order to record a high-definition image, therefore, if the frequency of a video clock signal (f.sub.c /8) is 20 MHz, the clock frequency f.sub.c is required to be 160 MHz. If the frequency of the video clock signal is increased to 30 MHz for increasing the scanning rate, on the other hand, the frequency of the original clock signal would become 240 MHz. A circuit for generating an original clock signal of such a high frequency and a frequency-dividing circuit are high in cost. Therefore, a clock signal generation apparatus for generating a high-frequency video clock has been expensive.
In the prior art, as disclosed in JP-A-58-126398 and JP-A-58-104565, an original clock signal is delayed by a delay circuit to produce a plurality of clock signals whose phase differences are different to one another, so that one of the plurality of clock signals with an optimum frequency is selected in response to a sync timing signal, and the selected clock signal is frequency-divided thereby to produce a video clock. This circuit comprising the delay circuit made up of an analog signal processing circuit, however, has posed the problem of a low stability since the delay time of the delay circuit fluctuates with temperature changes.
Further, if the frequency of the original clock signal changes, the delay time of respective delay elements of the delay circuit are required to be changed accordingly, thus necessitating a change of the delay circuit to another one.